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| W29EE512 64K x 8 CMOS FLASH MEMORY GENERAL DESCRIPTION The W29EE512 is a 512K bit, 5-volt only CMOS flash memory organized as 64K x 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29EE512 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. FEATURES * Single 5-volt program and erase operations * Fast page-write operations * Low power consumption - Active current: 50 mA (max.) - Standby current: 100 A (max.) * Automatic program timing with internal VPP - 128 bytes per page - Page program cycle: 10 mS (max.) - Effective byte-program cycle time: 39 S - Optional software-protected data write * Fast chip-erase operation: 50 mS * Read access time: 70/90/120 nS * Typical page program/erase cycles: 1K/10K * Ten-year data retention * Software and hardware data protection generation * End of program detection - Toggle bit - Data polling * Latched address and data * TTL compatible I/O * JEDEC standard byte-wide pinouts * Available packages: 32-pin PLCC and TSOP -1- Publication Release Date: March 1998 Revision A5 W29EE512 PIN CONFIGURATIONS BLOCK DIAGRAM VDD VSS A 1 2 4 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A 1 5 3 N C 2 N C 1 V/ CW CE N C CE OE WE 29 28 27 A14 A13 A8 A9 A11 OE A10 CE DQ7 CONTROL OUTPUT BUFFER DQ0 . . 32 31 30 DQ7 32-pin PLCC 26 25 24 23 22 21 A0 . . A15 DECODER CORE ARRAY D Q 1 DG QN 2D D Q 3 D Q 4 D Q 5 D Q 6 PIN DESCRIPTION A11 A9 A8 A13 A14 NC WE VCC NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 SYMBOL A0-A15 DQ0-DQ7 CE OE WE VCC GND NC PIN NAME Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Power Supply Ground No Connection 32-pin TSOP 25 24 23 22 21 20 19 18 17 -2- W29EE512 FUNCTIONAL DESCRIPTION Read Mode The read operation of the W29EE512 is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed. OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details. Page Write Mode The W29EE512 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded will be erased to "FFh" during programming of the page. The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage. During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE, whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 150 S, after the initial byte-load cycle, the W29EE512 will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional byte is loaded into the page buffer A7 to A15 specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required. In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. Before the completion of the internal programming cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page. Software-protected Data Write The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a series of three-byte program commands (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down. The W29EE512 is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte program command cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. A power transition will not reset the software data protection feature. To reset the device to unprotected mode, a six-byte command sequence is required. Publication Release Date: March 1998 Revision A5 -3- W29EE512 Hardware Data Protection The integrity of the data stored in the W29EE512 is also hardware protected in the following ways: (1) Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VCC Power Up/Down Detection: The programming operation is inhibited when VCC is less than 2.5V. (3) Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. Data Polling (DQ7)-Write Status Detection The W29EE512 includes a data polling feature to indicate the end of a programming cycle. When the W29EE512 is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is completed. DQ7 will show the true data. Toggle Bit (DQ6)-Write Status Detection In addition to data polling, the W29EE512 provides another method for determining the end of a program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. 5-Volt-only Software Chip Erase The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycles, the device enters the internal chip erase mode, which is automatically timed and will be completed in 50 mS. The host system is not required to provide any control or timing during this operation. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the device code (C8h). The product ID operation can be terminated by a three-byte command sequence. In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts. -4- W29EE512 TABLE OF OPERATING MODES Operating Mode Selection (Operating Range = 0 to 70 C (Ambient Temperature), VCC = 5V 10%, VSS = 0V, VHH = 12V) MODE CE Read Write Standby Write Inhibit Output Disable 5-Volt Software Chip Erase Product ID VIL VIL VIH X X X VIL VIL VIL OE VIL VIH X VIL X VIH VIH VIL VIL WE VIH VIL X X VIH X VIL VIH VIH AIN AIN X X X X AIN PINS ADDRESS Dout Din High Z High Z/DOUT High Z/DOUT High Z DIN Manufacturer Code DA (Hex) Device Code C8 (Hex) DQ. A0 = VIL; A1-A15 = VIL; A9 = VHH A0 = VIH; A1-A15 = VIL; A9 = VHH -5- Publication Release Date: March 1998 Revision A5 W29EE512 Command Codes for Software Data Protection BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write TO ENABLE PROTECTION ADDRESS DATA 5555H AAH 2AAAH 55H 5555H A0H TO DISABLE PROTECTION ADDRESS DATA 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 20H Software Data Protection Acquisition Flow Software Data Protection Enable Flow Load data AA to address 5555 Software Data Protection Disable Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 55 to address 2AAA Load data A0 to address 5555 Load data 80 to address 5555 (Optional page-load operation) Sequentially load up to 128 bytes of page data Load data AA to address 5555 Pause 10 mS Load data 55 to address 2AAA Exit Load data 20 to address 5555 Pause 10 mS Exit Notes for software program code: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) -6- W29EE512 Command Codes for Software Chip Erase BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H DATA AAH 55H 80H AAH 55H 10H Software Chip Erase Acquisition Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 10 to address 5555 Pause 50 mS Exit Notes for software chip erase: Data Format: DQ7-DQ0 (Hex) Address Format: A14-A0 (Hex) -7- Publication Release Date: March 1998 Revision A5 W29EE512 Command Codes for Product Identification BYTE SEQUENCE ALTERNATE SOFTWARE (5) PRODUCT IDENTIFICATION ENTRY ADDRESS 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 5555H 2AAAH 5555H - SOFTWARE PRODUCT IDENTIFICATION ENTRY ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H SOFTWARE PRODUCT IDENTIFICATION EXIT ADDRESS 5555H 2AAAH 5555H - DATA AAH 55H 90H - DATA AAH 55H 80H AAH 55H 60H DATA AAH 55H F0H - Pause 10 S Pause 10 S Pause 10 S Software Product Identification Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Product Identification Mode (2,3) Product Identification Exit (1) Load data 55 to address 2AAA Load data AA to address 5555 Load data 80 to address 5555 Read address = 0 data = DA Load data 55 to address 2AAA Load data AA to address 5555 Load data FO to address 5555 Load data 55 to address 2AAA Read address = 1 data = C8 Pause 10 S Load data 60 to address 5555 (4) Normal Mode Pause 10 S Notes for software product identification: (1) Data format: DQ7-DQ0 (Hex); address format: A14-A0 (Hex). (2) A1-A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification mode if power down. (4) The device returns to standard operation mode. (5) This product supports both the JEDEC standard 3 byte command code sequence and original 6 byte command code sequence. For new designs, Winbond recommends that the 3 byte command code sequence be used. -8- W29EE512 DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential except A9 Transient Voltage (O20 nS ) on Any Pin to Ground Potential Voltage on A9 and OE Pin to Ground Potential RATING -0.5 to +7.0 0 to +70 -65 to +150 -0.5 to VCC +1.0 -1.0 to VCC +1.0 -0.5 to 12.5 UNIT V C C V V V Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VCC = 5.0V 10%, VSS = 0V, TA = 0 to 70 C) PARAMETER SYM. TEST CONDITIONS LIMITS MIN. TYP. MAX. 50 UNIT Power Supply Current Standby Vcc Current (TTL Input) Standby Vcc Current (CMOS Input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage ICC CE = OE = VIL, WE = VIH, all I/Os open Address inputs = VIL/VIH, at f = 5 MHz - - mA ISB1 CE = VIH, all I/Os open Other inputs = VIL/VIH - 2 3 mA ISB2 CE = VCC -0.3V, all I/Os open Other inputs = VCC -0.3V/GND - 20 100 A ILI ILO VIL VIH VOL VIN = GND to VCC VIN = GND to VCC IOL = 2.1 mA 2.0 2.4 4.2 - 10 10 0.8 0.45 - A A V V V V V Output High Voltage VOH1 IOH = -0.4 mA Output High Voltage VOH2 IOH = -100 A; VCC = 4.5V CMOS -9- Publication Release Date: March 1998 Revision A5 W29EE512 Power-up Timing PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU.READ TPU.WRITE TYPICAL 100 5 UNIT S mS CAPACITANCE (VCC = 5.0V, TA = 25 C, f = 1 MHz) PARAMETER I/O Pin Capacitance Input Capacitance SYMBOL CI/O CIN CONDITIONS VI/O = 0V VIN = 0V MAX. 12 6 UNIT pF pF AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load CONDITIONS 0V to 3V < 5 nS 1.5V/1.5V 1 TTL Gate and CL = 100 pF/30 pF AC Test Load and Waveform +5V 1.8 Kohm D OUT 100 pF (For 90 nS/120 nS) 30 pF (For 70 nS) 1.3Kohm Input 3V 1.5V 0V Output 1.5V Test Point Test Point - 10 - W29EE512 Read Cycle Timing Parameters (VCC = 5.0V 10%, VCC = 5.0 5% for 70 nS, VSS = 0V, TA = 0 to 70 C) PARAMETER SYM. W29EE512-70 W29EE512-90 W29EE512-12 MIN. MAX. 70 70 35 25 25 MIN. 90 0 MAX. 90 90 40 25 25 MIN. 120 0 MAX. 120 120 50 30 30 - UNIT Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE High to High-Z Output OE High to High-Z Output Output Hold from Address Change TRC TCE TAA TOE TCHZ TOHZ TOH 70 0 nS nS nS nS nS nS nS Byte/Page-write Cycle Timing Parameters PARAMETER Write Cycle (Erase and Program) Address Setup Time Address Hold Time WE and CE Setup Time WE and CE Hold Time OE High Setup Time OE High Hold Time CE Pulse Width WE Pulse Width WE High Width Data Setup Time Data Hold Time Byte Load Cycle Time SYMBOL TWC TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH TBLC MIN. 0 50 0 0 0 0 90 90 100 35 0 TYP. MAX. 10 150 UNIT mS nS nS nS nS nS nS nS nS nS nS nS S Notes: All AC timing signals observe the following guidelines for determining setup and hold times: (1) High level signal's reference level is VIH. (2) Low level signal's reference level is VIL. - 11 - Publication Release Date: March 1998 Revision A5 W29EE512 DATA Polling Characteristics (1) PARAMETER Data Hold Time OE Hold Time OE to Output Delay (2) Write Recovery Time Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters. SYMBOL TDH TOEH TOE TWR MIN. 10 10 0 TYP. - MAX. - UNIT nS nS nS nS Toggle Bit Characteristics (1) PARAMETER Data Hold Time OE Hold Time OE to Output Delay (2) OE High Pulse Write Recovery Time SYMBOL TDH TOEH TOE TOEHP TWR MIN. 10 10 150 0 TYP. MAX. UNIT nS nS nS nS nS Notes: (1) These parameters are characterized and not 100% tested. (2) See TOE spec in A.C. Read Cycle Timing Parameters. - 12 - W29EE512 TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A15-0 CE TCE OE TOE WE VIH TOHZ TOH DQ7-0 High-Z Data Valid TAA TCHZ Data Valid High-Z WE Controlled Write Cycle Timing Diagram T WC TAS Address A15-0 TAH CE TCS TOES TCH T OEH OE TWP T WPH WE TDS DQ7-0 Data Valid TDH Internal write starts - 13 - Publication Release Date: March 1998 Revision A5 W29EE512 Timing Waveforms, continued CE Controlled Write Cycle Timing Diagram TAS TAH TWC Address A15-0 TCPH TCP CE TOES OE WE TDS DQ7-0 High Z Data Valid TOEH TDH Internal write starts Page Write Cycle Timing Diagram TWC Address A15-0 DQ7-0 CE OE TWP WE Byte 0 TWPH TBLC Byte 1 Byte 2 Byte N-1 Internal write starts Byte N - 14 - W29EE512 Timing Waveforms, continued DATA Polling Timing Diagram Address A15-0 WE CE TOEH OE TDH DQ7 TOE HIGH-Z TWR Toggle Bit Timing Diagram WE CE OE TOEH TDH TOE HIGH-Z TWR DQ6 - 15 - Publication Release Date: March 1998 Revision A5 W29EE512 Timing Waveforms, continued Page Write Timing Diagram Software Data Protection Mode Three-byte sequence for software data protection mode Address A15-0 5555 2AAA 5555 Byte/page load cycle starts TWC DQ7-0 AA 55 A0 CE OE WE TWP TWPH TBLC SW0 SW1 SW2 Word 0 Word N-1 Word N (last word) Internal write starts Reset Software Data Protection Timing Diagram Six-byte sequence for resetting software data protection mode Address A15-0 TWC 5555 2AAA 5555 5555 2AAA 5555 DQ7-0 AA 55 80 AA 55 20 CE OE WE TWP TWPH SW0 TBLC SW1 SW2 SW3 SW4 SW5 Internal programming starts - 16 - W29EE512 Timing Waveforms, continued 5-Volt-only Software Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase TWC Address A15-0 5555 2AAA 5555 5555 2AAA 5555 DQ7-0 AA 55 80 AA 55 10 CE OE WE TWP TWPH SW0 TBLC SW1 SW2 SW3 SW4 SW5 Internal programming starts - 17 - Publication Release Date: March 1998 Revision A5 W29EE512 ORDERING INFORMATION PART NO. ACCESS TIME (nS) 70 90 120 70 90 120 70 90 120 70 90 120 POWER SUPPLY CURRENT MAX. (mA) 50 50 50 50 50 50 50 50 50 50 50 50 STANDBY VCC CURRENT MAX. (A) 100 100 100 100 100 100 100 100 100 100 100 100 PACKAGE CYCLE W29EE512P-70 W29EE512P-90 W29EE512P-12 W29EE512T-70 W29EE512T-90 W29EE512T-12 W29EE512P-70B W29EE512P-90B W29EE512P-12B W29EE512T-70B W29EE512T-90B W29EE512T-12B Notes: 32-pin PLCC 32-pin PLCC 32-pin PLCC Type one TSOP Type one TSOP Type one TSOP 32-pin PLCC 32-pin PLCC 32-pin PLCC Type one TSOP Type one TSOP Type one TSOP 1K 1K 1K 1K 1K 1K 10K 10K 10K 10K 10K 10K 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 18 - W29EE512 PACKAGE DIMENSIONS 32-pin PLCC HE E 4 1 32 30 Symbol 5 29 Dimension In Inches Dimension In mm Min. 0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 Nom. Max. 0.140 Min. 0.50 Nom. Max. 3.56 GD DH D 13 21 14 20 c A A1 A2 b1 b c D E e GD GE HD HE L y 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090 0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10 L A2 A 0 10 0 10 Notes: 1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on fina visual inspection sepc. Seating Plane e b b1 A1 y G E 32-pin TSOP HD Symbol Dimension In Inches Min. Nom. Max. 0.047 0.006 0.041 0.009 0.007 Dimension In mm Min. Nom. Max. 1.20 0.15 1.05 0.23 0.17 18.50 8.10 20.20 D c A A1 A2 __ 0.002 0.037 0.007 __ __ 0.039 0.008 __ 0.05 0.95 0.17 0.12 __ __ 1.00 0.20 0.15 M e E b c D E HD e L L1 A A2 0.005 0.006 0.720 0.724 0.311 0.780 0.315 0.787 0.020 0.020 0.031 0.10(0.004) 0.728 18.30 18.40 0.319 7.90 8.00 20.00 0.50 0.50 0.80 b 0.795 19.80 __ 0.016 __ 0.024 __ 0.40 __ 0.60 __ 0.000 1 __ 0.004 5 __ 0.00 1 __ 0.10 5 Y __ 3 __ 3 L L1 A1 Y Note: Controlling dimension: Millimeters - 19 - Publication Release Date: March 1998 Revision A5 W29EE512 VERSION HISTORY VERSION A5 DATE Mar. 1998 PAGE 6 7 8 1, 2, 18, 19 Add. pause 10 mS Add. pause 50 mS Correct the time from 10 mS to 10 S Eliminate 600 mil DIP, 450 mil SOP packages DESCRIPTION Headquarters Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5796096 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. - 20 - |
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